As semi-conductor processes continue to scale, the number of transistors available in a silicon-chip increases. Integrating the whole system on a chip becomes a possibility for many applications. However, multiple systems are composed of many separate components such as DRAM, EEPROM, and FLASH which are fabricated using specialized processes. These processes may not be compatible with the common logic process used for manufacturing logic components such as micro-processors and system logics.
Common logic or application-specific-integrated-circuit (ASIC) processes are typically the most aggressively scaled processes offered by silicon foundries. In order to integrate specialized memory components (e.g., EEPROM, DRAM and FLASH) on the same substrate as logic components, additional processing steps may need to be added to a logic process. However, adding steps to logic manufacturing processes adds to the manufacturing cost of all the components of the chip, including the logic components.
Alternatively, memory circuits may need to be designed to be compatible with the logic process. Designing memory circuits to be compatible with logic processes are therefore more desirable, especially for chips in which logic circuits occupy the majority of the chip area.
The common logic processes offered by silicon foundries with feature sizes in a very deep submicron (e.g., 130 nm and 90 nm) area may include the following characteristics: 1) single-layer poly-silicon; 2) transistors with thin oxide for the logic circuits operating at a lower supply voltage (e.g., 1.0 v) and transistors with thick oxide for handling higher 10 voltages (for example 3.3 v); 3) Deep N-well for the isolation of the n-channel transistors used in noise sensitive circuits such as clock synchronizers.
Although prior art methods have attempted to build non-volatile memories (e.g. EEPROM, FLASH) using logic processes, each include limitations that may result in a need for special circuits, a larger cell size, compromised data retention, added power costs, and/or added manufacturing complexity.
For example, a memory cell may include a PMOS transistor and an NMOS coupling capacitor, the bulk of which is connected to a substrate that is common with a logic circuit. The substrate of the memory cell is in multiple cases connected to ground or 0 v. In this configuration, the memory may require a relatively high voltage (e.g., 6.5 v or higher) connected to the source or drain of the PMOS transistor. Without high-voltage transistors, a special circuit technique may be required to build on-chip programming circuits that are capable of tolerating the relatively high voltage used for programming the memory cell. In addition, to facilitate Fowler-Nordheim tunneling at the relatively high voltage, the oxide thickness of the transistors may be limited, making data retention less reliable. This memory cell may therefore also require special circuits to enhance data retention time.
Additional variants of memory cells exist, each of which may include various limitations. For example, a type of single-poly EPROM memory cell may not be erased electrically. An additional type of memory cell may require two NMOS transistors, and may require hot-hole injection into the floating gate and hot-electron injection into the floating gate. In another type of memory cell, a spacer nitride next to a poly gate may be required to trap hot carriers generated during a programming and an erase operation of the memory cell.
An additional type of memory cell may require the use of three transistors and a shared floating gate to form an access device, a program device, and a coupling capacitor of a memory cell. An additional type of memory cell may require four MOS devices. An alternate memory cell may require that a coupling device operate with a capacitance smaller than the gate capacitance of an access device of the memory cell. Another type of FLASH memory cell may require being formed with a N+ region under a floating gate where the N+ region is continuous with a diffusion word line. The N+ region may require an additional implant that cannot be formed as part of the logic process.
An additional type of memory cell may require the use of a coupling capacitor with two charge injection regions. The memory cell may also be deposed directly on the substrate, which may restrict the source and drain voltage from being set more positive than the logic supply voltage or more negative than ground. This may severely limit cells that are constrained to critical dimensions of 130 nm or smaller. Yet another type of memory cell may require the use of a PMOS transistor and a PMOS coupling capacitor. It would therefore be desirable to have a non-volatile memory cell that avoids the limitations of the prior art.